A new partition with 14 compute nodes holding NVIDIA H200 GPUs with 141 GB HBM memory is installed to satisfy the growing needs for AI-workloads at NHR@ZIB.

The extended compute partition based on AMD CPUs is available for all users. The new partition consists of 250 compute nodes. Each node contains 2 CPUs, each an AMD EPYC 9654 Genoa with 96 cores, and 1.5 TB of main memory. The network is 400 Gb/s InfiniBand but the shared IO configuration effectively yields 200 Gb/s per node.

On system Lise, NHR@ZIB has installed a new parallel storage system for the file systems Home and Work. All projects together have access to 20 PByte disk storage via the parallel file system IBM Storage Scale. The system supports quotas for volume and inodes, for groups and users respectively. The quotas can be configured per directory and include soft and hard limits as well as grace periods.

The new compute partition based on AMD CPUs is available for all users. Each node contains 2 CPUs, each an AMD EPYC 9654 Genoa with 96 cores, and 1.5 TB of main memory. The network is 400 Gb/s InfiniBand but the shared IO configuration effectively yields 200 Gb/s per node. We plan to provide the AMD CPU partition nearly free of charge till end of 2024 as the usage situation supports it.

The HPC system Lise and its DAOS storage system achieved rank 3 on the ten node production list of the IO500 list. For more information, please read the article on the ZIB website.

ZIB, ParTec and Next Silicon are excited to invite you to the upcoming technical Accelerator Hackathon. Join us in this 1.5 day hackathon to learn about the exciting new HPC approach from NextSilicon. This deep dive covers the programming environment, profiling analysis and optimization approach with dedicated hands-on sessions to allow participants to experience this novel hardware directly. The hackathon will take place

• at Zuse Institute Berlin
• from March 21st to March 22nd 2024.

For more information, please visit the workshop page.

Introduction to parallel programming with MPI and OpenMP
March 11-15 2024

lecturer: Matthias Läuter
location: Technische Universität Berlin and NHR at Zuse Institute Berlin
language: German
details and registration: TU-Berlin

NHR@ZIB is happy to announce the availability of the first publicly available Intel GPU partition in Germany.

Eight nodes, each equipped with four Intel Data Center GPU Max 1550 (also known as  Ponte Vecchio/PVC), two 56-core Intel “Sapphire Rapids” Xeon CPUs, 1 TB of RAM, and 3.6 TB of local NVMe storage are now available for all users.

The new partition allows users to run GPU workloads programmed in a cross-platform approach using OpenMP offloading (C/C++/Fortran) or SYCL  (C++ only). Both approaches are supported by Intel’s oneAPI which is available on the partition. Codes programmed in OpenMP or SYCL allow execution on both Nvidia and Intel (as well AMD) GPUs. The migration of  existing CUDA codes to SYCL can be assisted by tools. For AI workloads, PyTorch, TensorFlow, and (experimental) JAX are supported by oneAPI as well.

With Lise’s existing A100 partition, NHR@ZIB provides the great opportunity to explore and compare both architectures within the same HPC system. For more information please visit the

User Manual for Lise partitions

we have refreshed the online presence for the system Lise in Berlin. You can find

• general information on nhr.zib.de,
• the User Manual on user.nhr.zib.de, and
• the Portal NHR@ZIB (for project and account management) on portal.nhr.zib.de.

Best regards
NHR@ZIB

Parallel programming day
January 2024

lecturer: Dr. Christian Köhler (NHR@GWDG), Dr. Matthias Läuter (NHR@ZIB), Dr. Lewin Stein (NHR@ZIB)
details and registration: workshop page